1. Field of the Invention
The invention relates to synchronous/asynchronous communications controllers. Furthermore, the invention relates to phase locked loop circuits.
2. Description of the Relevant Art
BAUD rate generators and phase locked loop circuits each have many applications. In certain of these applications, such as communications apparatus for computer systems, both a BAUD rate generator and a phase locked loop are required. A UASRT (Universal Asynchronous Synchronous Receiver Transmitter) is one such device which typically requires both a BAUD rate generator and a phase locked loop. A designer of a UASRT circuit thus incorporates a BAUD rate generator and a phase locked loop within the UASRT and treats them as separate units.
Communication controllers allow modern computers to accept data or instructions originating from a plurality of remote terminals or from other computers. The term "communications controller" is used for a variety of communications peripherals, including UASRTs, which control the transmission and reception of data and typically perform a number of additional tasks.
Almost all computer systems are logically organized to transmit data between the central processing unit (CPU), memory, and peripheral devices in words or characters consisting of a plurality of bits in parallel. Remote terminals which are to communicate with the computer system, on the other hand, must use serial transmission since only this type of transmission channel is available from common carriers such as modems. Virtually all computer communications are, therefore, standardized with the serial transmission of data.
Additional bits and characters may be incorporated into the serial data stream for synchronization and control purposes. The data, in addition to these inserted control bits and characters, is oriented in a serial bit string at a transmitting port. The serial bit string is received at a receiving port where it is reconverted to form the original data characters with the support of the inserted control bits and characters. This process is transparent to the end user for whom the serial link is a mechanism for transmitting parallel data.
The interconnection of computers and terminals over serial communication mechanisms therefore requires several basic functions including the following: conversion of data from parallel form to serial form at the transmitting end, the conversion of data from serial form to parallel form at the receiving end, the insertion of control bits and characters for data synchronization and error control on the transmitting end, and the interpretation of these control bits and characters on the receiving end.
As the size and complexity of data communication networks have increased, more sophisticated units have been developed which perform a number of additional tasks. Examples of such additional tasks include: 1) line polling; 2) auto-BAUD (automatic speed) detection; 3) ability to handle many different line protocols; 4) code conversion (e.g., ASCII to EBCDIC or vice versa); 5) message assembly and simple editing; 6) error correction; 7) data compression; 8) simple syntax checking; 9) automatic loading and restart of remote computers and terminals; 10) data buffering, multiplexing, and concentrating; 11) automatic gathering of network statistics, including error logging; and 12) network diagnostics.
Many newer communications controllers are user programmable. Such controllers help to reduce the overhead by handling many of the tasks which were formerly handled by the host computer. These controllers are often more flexible than older controllers in that they can be programmed to perform new functions or support new types of terminals. Moreover, in many cases, programming of such units is much simpler than embedding the same functions into a complex operating system on the host.
To accommodate widespread use, manufacturers design communications controllers to be easily interfaced with a large variety of terminals and data types. Different terminals and data types often have varying data rates, may be buffered or unbuffered, local or remote, and operate in synchronous or asynchronous modes. To accommodate each of these variants, the input/output structure of a controller should be very flexible. For high speed lines, special channels with direct memory access (DMA) are desirable. Such channels can access memory on a cycle stealing basis and require no interventions by the processor once the transfer is initiated.
A communications controller that operates in an asynchronous mode typically includes a programmable BAUD rate generator to convert an incoming data stream to parallel data. In asynchronous mode, start bits are used to signal the start of a character. The phase of the sampling clock that is used to select when the received data stream is sampled by the input circuitry is determined by the initial edge of the start bit which precedes each character transmitted and which can occur at any time. The BAUD rate generator produces a BAUD rate signal which is used to determine the rate at which an incoming signal is sampled. Sampling circuitry accordingly samples the incoming signal at the rate of the BAUD rate signal and in accordance with the phase of the start bits. The sampling circuitry finally converts the received data stream to parallel data.
A communications controller that operates in a synchronous mode typically includes a digital phase locked loop (DPLL) circuit that contains a programmable BAUD rate generator to convert the received data stream to parallel data. In synchronous mode, the DPLL provides a sampling clock to the sampling circuitry that is phase-locked with the received data stream. This allows the input circuitry to place the character bits in their proper positions in the bit stream without the requirement of start and stop bits.
FIG. 1 shows a block diagram of a portion of a UASRT circuit wherein a BAUD rate generator and a digital phase locked loop (DPLL) are incorporated as separate units. A multiplexer 14 selects either an external clock or the system clock to go to multiplexer 11. Multiplexer 11 selectively couples a clock signal or a divided clock signal to the BAUD rate generator 10 and the digital phase locked loop 12. The output lines of BAUD rate generator 10 and DPLL 12 are connected to a sampling circuit 13. Sampling circuit 13 is programmed to select the BAUD rate generator clock signal or the DPLL clock signal to sample the received data stream.
When the UASRT shown in FIG. 1 operates in an asynchronous mode, BAUD rate generator 10 is programmed to generate a BAUD rate clock signal indicative of the divided or undivided clock signal coupled through multiplexers 11 and 14. Sampling circuit 13 is programmed to select this BAUD rate clock signal as the sampling clock and to sample the received data stream. During asynchronous mode, the DPLL clock signal is not used by sampling circuit 13 and may not be generated by DPLL 12.
When the UASRT operates in the synchronous mode, the DPLL 12 provides the sampling clock (DPLL clock signal) to sampling circuit 13. DPLL 12 contains phase adjusting circuitry, which, depending on the edges of the received data stream, makes phase adjustments to produce the DPLL clock signal. During synchronous mode, the BAUD rate generator clock signal is not used by sampling circuit 13 and may not be generated by BAUD rate generator 10.
In order to generate a sampling clock signal having a certain BAUD rate and phase, a digital phase locked loop such as DPLL 12 commonly utilizes a count register which contains values incremented or decremented from a start value to a stop value. When the value in the count register reaches the stop value, the count register is reset to its start value and the sequence repeats. This counting sequence determines the BAUD rate. Phase adjustments are accomplished by adjusting the value in the count register an amount based on the difference between the time at which transitions of an incoming signal occur, and the time at which the DPLL repeats the sequence to generate another cycle of the sampling clock signal.
It has been an on-going developmental objective within the electronics industry to minimize the overall size of and number of components required in a circuit to perform a particular task. Accordingly, a BAUD rate generator circuit and a digital phase locked loop circuit are desirable that may be used in applications such as computer communications and that require a minimal overall size and number of components.